In the development of new receivers for television, more advanced signal processing techniques will be implemented in the circuitry of the video processing section. It has been proposed that such advanced video signal processing can be carried out by high-speed two-dimensional (2-D) spatial filtering or by three-dimensional (3-D) temporal filters. See for example, "Digital Signal Processing in Television Receivers" by M. J. J. C. Annergarn, A. H. H. J. Nillesen, and J. G. Raven, Philips Tech. Rev. 42, No. 6/7, 183-200, April 1986. Newer receivers will display pictures that have higher pixel resolution. For what has been termed High Definition Television (HDTV), if the processing is done in real-time, that is, at the same rate as the effective sampling rate of the picture, processing rates in excess of 80 million pixels/sec would be required (e.g. 1000 lines/field.times.50 fields/sec, 5:3 aspect ratio).
In the past analog signal processing techniques such as noise coring, edge peaking, and comb filter separation of luminance and chrominance signals have been based on one-dimensional time domain approaches implemented as simple Finite Impulse Response (FIR) signal processing structures. These have been quite limited as to the type of signal processing and enhancement operations that could be performed by the characteristic type of apparatus that resulted from following that approach.
More sophisticated signal processing is possible by means of the direct application of techniques for filtering 2-D data, known from the field of Mathematical Image Processing Theory. Various techniques for the enhancement of digital images are usually implemented by programming a general purpose computer to operate on stored digitized images off-line. These 2-D filtering techniques can be implemented in real-time by means of dedicated hardware. See for example, "High-Speed Architectures for Digital Image Processing", by A. N. Venetsanopoulos, K. M. Ty, and A. C. P. Loui, IEEE Trans. on Circuits and Systems, Vol. CAS-34., No. 8, 887-895, August 1987.
Due to hardware constraints, conventional designs of dedicated 2-D filters have favoured FIR filters even though IIR (Infinite Impulse Response) filters are known to be more efficient allowing lower order realizations than their FIR counterparts.
Considerations of hardware complexity, physical size of apparatus, power consumption, and economical manufacture are all of vital importance in any practical signal processing apparatus intended for use in consumer products.
The present invention introduces a dedicated hardware apparatus for real-time 2-D filtering which is based on a semi-systolic analog structure realization. The hardware realization is based directly on the 2-D digital transfer function H(z.sub.1,z.sub.2) and utilizes off-the-shelf components. Both FIR and the more efficient IIR filtering structures can be realized with this approach and high real-time rates can be attained through the use of analog components that have inherently small delay times. Also since the structures are semi-systolic they have advantages for VLSI implementation such as modularity, regularity, and high parallelism.
Recently, motion adaptive digital filters have been proposed for use in high-definition television video signal processing. These can be regarded as common 3-D FIR filters, for the implementation of techniques for video signal processing. They require delays of one or more field periods, such delays being accomplished by means of frame-stores. Since pixels in separate fields are combined, this type of signal processing is referred to as temporal filtering and can only be performed on those pixels for which no motion in the scene of the picture being displayed has occurred between fields. Thus the development of such a filter is complicated by the necessary inclusion of circuitry that implements a motion detection algorithm. The embodiments of apparatus arising out of the present invention do not require analog to digital (A/D) and digital to analog (D/A) converters, often used in conjunction with analog pre-filters and post-filters, to convert video signal data from analog raster scanned form to sampled digital data for processing; nor do they require expensive frame-stores or motion detection circuitry.
Other methods of performing real-time 2-D signal processing have been based on elaborate algorithms such as the Burt Pyramid which separates an image into a number of 2-D spatial frequency bandpass images. See for example, "A Two-Dimensional Real-Time Video Pyramid Processor", by J. H. Arbeiter and R. F. Bessler, RCA Review, Vol. 47, 3-31, March 1986. This method, although capable of real-time operation, has the disadvantage of greater complexity relative to the present invention, due to the need to process multiple bands and to generate a set of component images. When embodied in digital hardware, a large amount of circuitry is required along with the need for A/D, and D/A converters.
Theoretical aspects of the present invention have been described in "Realization of 2-D IIR Filters using Sample-and-Hold Circuitry", by M. A. Sid-Ahmed, 1991 IEEE International Symposium on Circuits and Systems, Vol. 5, June 1991, pp. 2467-2470.
This application encompasses both theoretical as well as actual hardware implementation which is the combined work of both applicants.